The telecommunications industry uses serial data transmission to move large amounts of data from one point to another. Both conventional Plesiochronous Digital Hierarchy (PDH) (i.e., T1/E1, T3/E3, etc.) and conventional Synchronous Optical Network/Synchronous Digital Hierarchy (SONET/SDH) systems multiplex or aggregate multiple source streams together to allow a single serial stream to carry multiple lower speed sources. The conventional systems multiplex the source streams based upon character boundaries that force additional latency into the system to allow the channels to be interleaved.
Recent backplane designs for transporting the source data streams are using bit interleaving to reduce the latency, and lower the hardware overhead needed to handle the multiplexing and demultiplexing functions. Each source data stream is accepted as a serial stream, and the bits of each source data stream are sequentially bit-wise interleaved or aggregated to generate a single faster bit stream. Multiplexing ‘n’ source data streams together produces a serial data stream that is n-times faster than each of the source data streams.
Where the aggregation function is desired but a logic overhead and delay of full framers are not available or wanted, the aggregation function can still occur by doing a bit-level or byte-level multiplexing of the individual source data streams. Since there are generally no distinguishing characteristics within the data itself to identify which source data stream is which, and the fact that more than one of the source data streams can theoretically be carrying the same data, there needs to be some way to distinguish each of the source data streams for separation at the receiver. Furthermore, there needs to be some way to resolve the received source data stream into particular lanes. When the single higher-speed serial data stream arrives at the destination, the ‘n’ source data streams need to be separated. Standard clock recovery, data recovery, and demultiplex functions can provide the separation, but the extracted (de-interleaved) serial data streams have no default orientation as to which source data stream should come out on a specific output bit-stream or lane.
Referring to FIG. 1, a block diagram of a conventional data stream interleaving and de-interleaving system 10 is shown. The system 10 inverts 12 a master source data stream (i.e., J) among several source data streams (i.e., J–M) in a transmitter 14 prior to a serializer 16. The serializer 16 interleaves the source data streams J–M into a channel stream (i.e., T) that is transmitted through a channel 18. The inversion 12 is effectively a lossless and reversible form of data manipulation that allows the master source data stream J to be identified from the other source data streams K–M at a receiver 20.
At the receiver 20, the channel stream T is separated into multiple destination streams (i.e., P–S) using a deserializer 22. The destination streams P–S are passed to a barrel shifter 23 to allow each of the possible destination streams P–S to be allocated to one of several lanes 24a–d. The particular destination stream P–S routed through the lane 24a is then inverted 26 to produce an inverted stream (e.g., W). The inverted stream W is tested for characteristics of the master source data stream J. Testing involves scanning 28 the inverted stream W for a specific frame construct that may be present. If the frame construct is not found, the barrel shifter 23 is ordered to rotate 30 to route a next destination stream P–S through the inverter 26. Scanning 28 and rotation 30 are continued until the specific frame construct is found in the inverted stream W. In practice, the non-inverted source data streams K–N should not generate a match condition when inverted 26. However, the inverted master source data stream J (after the secondary inversion 26) will allow proper detection of the frame construct.
The system 10 works while the four source data streams J–M are always present. However, SONET/SDH equipment does not provide for each source data stream J–M to originate from the same card, nor to be active all at the same time. Therefore, it is possible for one or more of the source data streams J–M to be missing or void of valid information. If a channel generating the master source data stream J ever goes away, the receiver 20 has no way of identifying the proper destination of the resulting destination data streams P–S. Therefore, allocating the destination streams P–S among the proper lanes 24a–d becomes impractical.